PSO-based charge pump chip area minimization

Abstract : In this paper a solution of the well-known silicon area/performance dilemma and an energy harvesting circuit for wireless sensor nodes are presented. A PSO-based integrated circuit area optimization methodology is proposed. The study is performed on a charge pump circuit, using a 0.35μm Si-CMOS process. The PSO sizing strategy has been implemented using a Spice kernel and Matlab environment. The chip size has been reduced from 583μm2 to 179μm2 after the optimization process. Simulation results from the 0.35μm parameters are given. When driving a capacitive load of 50pF, the output-generated voltage is 4V from a 1.3V input voltage. The simulated pumping gain is 3.1.
Type de document :
Communication dans un congrès
2012 International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD), Sep 2012, Séville, Spain. pp.133--136, 2012, 〈10.1109/SMACD.2012.6339435〉
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http://hal.univ-reunion.fr/hal-01202282
Contributeur : Réunion Univ <>
Soumis le : samedi 19 septembre 2015 - 16:46:15
Dernière modification le : mardi 27 février 2018 - 11:54:24

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Frédéric Alicalapa, Jean-Daniel Lan Sun Luk, Rahma Hajtaieb Aloulou, Hassene Mnif, Mourad Loulou. PSO-based charge pump chip area minimization. 2012 International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD), Sep 2012, Séville, Spain. pp.133--136, 2012, 〈10.1109/SMACD.2012.6339435〉. 〈hal-01202282〉

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